November 28th, 2022

Seoul National University to Present a UVM SystemVerilog Testbench for 5G/LTE Multi-Standard RF Transceiver

Scientific Analog, Inc. is pleased to announce that the researchers of Seoul National University, Seoul, Korea will be presenting a paper titled, "A UVM SystemVerilog Testbench for 5G/LTE Multi-Standard RF Transceiver," at the upcoming 2022 Design and Verification Conference and Exhibition Europe (DVCon Europe 2022), held in Munich, Germany on December 6-7, 2022.

The paper demonstrates how to use UVM to thoroughly verify a highly-reconfigurable analog/mixed-signal system supporting 351 operating modes. By describing a fixture module enclosing the multi-standard RF transceiver model and the analog instrumentations to supply stimuli and measure responses using XMODEL primitives, one can compose the rest of the testbench using standard UVM components, performing data checks, connectivity checks, and control signal checks with 100% coverage. The paper will be presented at 13:15pm on Wednesday, December 7, 2022 in Session P1.2.

"This paper provides a clear evidence that XMODEL is the best way to verify large-scale analog/mixed-signal systems in SystemVerilog," said Jaeha Kim, CEO and founder of Scientific Analog.

Scientific Analog, Inc. is a leading developer and provider of a mixed-signal simulator in SystemVerilog (XMODEL), automatic model generator (MODELZEN), and schematic-based design environment (GLISTER). DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies.

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