September 2023

Modeling a clocked comparator latch with reset, sampling, and regeneration behaviors

Can you model a regenerative amplifier with analog outputs performing reset, sampling, and regeneration? No, a transistor-level model doesn’t count.

Check out how to model a DAC showing a first- or second-order settling response with limits on its slew rate.

This primitive lets you set the maximum and minimum limits on the current that flows through a branch.

Modeling an Oscillator with Resettable Phase, Multiple Outputs, and Arbitrary Waveforms

UVM Testbench for LDOs, Modeling a Buffer with Variable Rise/Fall Delays, and More

XMODEL at DVCon US, Modeling D-PHY Transceivers, and More

Modeling a Buffer with Arbitrary Rising and Falling Transition Waveforms, and More

XMODEL at ASP-DAC 2024, Modeling Time-of-Flight Sensors, and More