April 18th, 2022

Jaeha Kim Talks on Efficient Analog/Mixed-Signal Simulation in SystemVerilog with Auto-Generated Models at CICC 2022

Jaeha Kim, the CEO and Founder of Scientific Analog, is giving a talk titled, “Efficient Simulation of Analog/Mixed-Signal Circuits in SystemVerilog with Auto-Generated Models” at the 2022 Custom Integrated Circuits Conference (CICC). The talk is scheduled at 9:00 am PDT on Sunday, April 24, 2022, and addresses ways to auto-extract models from analog circuits and run efficient simulations with them in an event-driven logic simulator like SystemVerilog.

Scientific Analog, Inc. is a leading developer and provider of a mixed-signal simulator in SystemVerilog (XMODEL), automatic model generator (MODELZEN), and schematic-based design environment (GLISTER).

The IEEE Custom Integrated Circuits Conference (CICC) is a premier conference devoted to IC development. CICC is sponsored by the IEEE Solid-State Circuits Society and technically co-sponsored by the IEEE Electron Devices Society.

Further information about this event can be found on its official website.

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